The present invention relates to a D/A (Digital-to-Analog) converter and, more particularly, to a D/A converter using a two-stage binary weighted capacitor ladder network.
A D/A converter using a binary weighted capacitor ladder network is suitable for an integrated D/A converter. Such a D/A converter using a two-stage weighted capacitor network has advantages in a smaller number of unit capacitors, a smaller occupying area on a D/A converter IC, and low fabrication cost as compared with a one-stage weighted capacitor network. U.S. Pat. No. 4,077,035 (Feb. 28, 1978) describes a two-stage binary weighted capacitor network comprising an integrator and two similar groups of capacitors connected in parallel. However, this network requires an operational amplifier since the network includes the integrator, resulting in a complicated circuit arrangement and large current consumption.
Another conventional D/A converter using a two-stage binary weighted capacitor network as shown in FIG. 1 is described in "Integrated PCM Codec", IEEE Journal Solid State Circuits, SC-14, PP. 38-46, Feb. 1979. This D/A converter does not include an operational amplifier.
Referring to FIG. 1, capacitors C.sub.0 to C.sub.l constitute a first stage capacitor ladder 1. These capacitors C.sub.0 to C.sub.l have binary weighted capacitances as follows: C.sub.0 =1.C, C.sub.1 =2.sup.0.C, C.sub.2 =2.sup.1.C, C.sub.3 =2.sup.2.C, . . . C.sub.l .dbd.2.sup.l-1.C where C is the capacitance of the unit capacitor. Capacitors C.sub.l+1 to C.sub.l+m constitute a second stage capacitor ladder 2. These capacitors C.sub.l+1 to C.sub.l+m have binary weighted capacitances as follows: C.sub.l+1 =2.sup.0.C, C.sub.l+2 =2.sup.1.C, C.sub.l+3 =2.sup.2.C, . . . C.sub.l+ =2.sup.m-1.C. The first and second capacitor ladders are coupled by a coupling capacitor C.sub.c of a capacitance C.sub.c.C to constitute a two-stage binary weighted capacitor network. One of the electrodes of the capacitances C.sub.1 to C.sub.l and C.sub.l+1 to C.sub.l+m is grounded or connected to a reference voltage V.sub.R through a corresponding one of switches S.sub.1 to S.sub.l and S.sub.l+1 to S.sub.l+m. The switches S.sub.1 to S.sub.l are controlled by less significant l bits of a digital input signal. The switches S.sub.l+1 to S.sub.l+m are controlled by more significant m bits of the digital input signal. The D/A converter serves as an (l+m)-bit D/A converter.
An output voltage V.sub.0 of the D/A converter shown in FIG. 1 is calculated on the basis of charge conservation as follows: ##EQU1## where b.sub.k is the coefficient of 0 or 1 determined in response to an (ll+m)-bit digital input signal, and V.sub.R is the reference voltage. In order to arrange the circuit as the (l+m)-bit D/A converter, the coupling capacitance C.sub.c must be given as follows: EQU C.sub.c ={2.sup.l /(2.sup.l -1)}C (2)
If equation (2) is satisfied, a substitution of equation (2) into equation (1) yields the output voltage V.sub.0 as follows: ##EQU2## Equation (3) can be rewritten as follows: ##EQU3## therefore, the analog output voltage V.sub.0 corresponding to the (l+m)-bit binary digital signal is obtained. The circuit in FIG. 1 serves as the (l+m)-bit D/A converter if the following condition is satisfied: EQU C.sub.c {2.sup.l /(2.sup.l -1)}C
However, it is difficult to obtain the coupling capacitance C.sub.c which constantly and perfectly satisfies equation (2).
For example, if l=6, then EQU C.sub.c /C=2.sup.6 /(2.sup.6 -1)=64/63=1.01587
It is difficult to accurately obtain the C.sub.c value, and thus precise digital-to-analog conversion precision cannot be obtained.